CONCURRENCY & VLSI
CS 139 a. Concurrency in Computation. 9 units (3-0-6); third term. Prerequisite: CS 20 or equivalent. Design and verification of concurrent algorithms. Topics: different models of concurrent computations; process synchronization by shared variables and synchronization primitives; distributed processes communicating by message exchange; the concepts of synchronization, indivisible actions, deadlock, and fairness; semantics and correctness proofs; implementation issues; and application to VLSI algorithm design. Parallel machine architecture issues include mapping a parallel algorithm on a network of processors, and classical parallel algorithms and their complexity.
CS 181 abc. VLSI Design Laboratory. 12 units (3-6-3); first, second, third terms. Digital integrated systems design, with projects involving the design, verification, and testing of high-complexity CMOS microcircuits. First-term lecture and homework topics emphasize disciplined design, and include CMOS logic, layout, and timing; computer-aided design and analysis tools; and electrical and performance considerations. Each student is required in the first term to complete individually the design, layout, and verification of a moderately complex integrated circuit. Advanced topics second and third terms include self-timed design, computer architecture, and other topics that vary year by year. Projects are large-scale designs done by teams. Class website.
CS 185 abc. Asynchronous VLSI Design Laboratory. 9 units (3-3-3); first, second, third terms. Prerequisite: CS 139. The design of digital integrated circuits whose correct operation is independent of delays in wires and gates. (Such circuits do not use clocks.) Emphasis is placed on high-level synthesis, design by program transformations, and correctness by construction. The first term introduces delay-insensitive design techniques, description of circuits as concurrent programs, circuit compilation, standard-cell layout and other computer-aided design tools, and electrical optimizations. The second term is reserved for advanced topics, and for the presentation and review of mid-size projects. Complete projects will be fabricated in CMOS via MOSIS and tested.
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Mailing Address: Alain Martin, Department of Computer Science, Caltech 256-80, Pasadena CA 91125, USA.
This research is supported by the National Science Foundation.
Last Modified: 07 Dec 2006