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ASYNCHRONOUS VLSI CHIPS @ CALTECH
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The design of an asynchronous pipelined Lattice-Structure Filter, in 1994, was the occasion for experimenting with very fine pipelines. It is a programmable FIR filter of 1 to 80 coefficients. Samples and coefficients are 12 bits. The chip has 250K transistors. The experiment was encouraging: In 0.9 µm CMOS and at 3.3V the throughput is 130MHz, which correspond to 500 millions operations per second, where an operation is a 12-bit addition or multiplication. In liquid nitrogen, the filter executes 1 billion operations per seconds.

Measurements show that the chips work correctly from 1V to 5V and from 77K to 400K. At 1.1V, the chip operates at 36 Mops and consumes 0.02W.

The filter is described in this 1994 Async conference paper.


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Mailing Address: Alain Martin, Department of Computer Science, Caltech 256-80, Pasadena CA 91125, USA.
This research is supported by the National Science Foundation.
Last Modified: 07 Dec 2006