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ASYNCHRONOUS VLSI
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"Delays have dangerous ends."
- William Shakespeare -

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A physical implementation of a digital computation is said to be asynchronous when it does not use a clock for sequencing the steps of the computation. Instead, sequencing is implemented by local communication among adjacent computation steps.

Asynchronous & QDI Logic

An asynchronous VLSI system is a distributed system on a chip whose concurrent components communicate with each other and synchronize their activities by message exchange. Communication is implemented by handshake protocols. There is no concept of global time - no clocks are used - and only minimal assumptions are made about the duration of an action or of a communication.

Various approaches to asynchronous logic differ by the timing assumptions they introduce. The Caltech approach has been to make as few timing assumptions as possible. For a time it was believed possible to design entirely delay-insensitive asynchronous circuits until we proved that the class of such circuits is very limited. See our 1990 MIT ARVLSI conference paper. Instead, Caltech has developed a class of asynchronous circuits we called quasi delay-insensitive or QDI. A QDI circuit does not use any assumption on, or knowledge of, delays in operators and wires, with the exception of some forks, called isochronic forks.

QDI circuits are the most conservative asynchronous circuits in terms of the use of delays. But they are also the most robust to physical parameters variations because the circuit's dependence on delays is minimal. It is this robustness that makes it possible to exchange energy and throughput against each other through voltage adjustments. Experiments in QDI design have also shown that extra delay assumptions (like, e.g. bundled data) are not necessary to achieve high performance. QDI is now widely used, also in industry.

Why Asynchronous Circuits?

From the early days, research in asynchronous logic has been motivated by both practical reasons: "Can we get rid of the clock?" and theoretical ones: "What is the role of time in the physical implementation of computation?". Those reasons are still valid. But other important advantages of QDI logic have become apparent. Read more...

An overview of the research in Asynchronous VLSI at Caltech as of 2007 can be found in this Powerpoint presentation. A good introduction to QDI design can be found in this IEEE Proceedings paper.

To see some of the circuits designed by the Caltech group, please visit the chips page.

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Back to Asynchronous VLSI Group Home
Mailing Address: Alain Martin, Department of Computer Science, Caltech 256-80, Pasadena CA 91125, USA.
This research is supported by the National Science Foundation.
Last Modified: May 2008