Siddharth Bhargav

Visiting Graduate Student - California Institute of Technology


I am Siddharth Bhargav, A Special graduate student at Asynchronous VLSI group under Prof.Alain J Martin here at the department of Computer Science at the CalTech and a PhD Student at the department of Electrical Engineering at the University of Southern California, Los Angeles.


  • Hspice
  • Berkeley SIS
  • Verilog
  • HDL
  • PERL/Python
  • C++


Phd Student - Electrical Engineering

Jan 2010 To Present

University Of Southern California, Los Angeles - UNITED STATES

Visiting Graduate - Computer Science

May 2009 To Present

California Institute Of Technology, Pasadena - UNITED STATES

Master Of Science - Electrical Engineering

Aug 2008 To Dec 2009

University Of Southern California, Los Angeles - UNITED STATES

Bachelor Of Engineering - Electronics & Communication

Oct 2002 To June 2006

JSS Academy Of Technical Education, Bangalore - INDIA



  • Research Assistant

    1. At USC-ISI : Prof.Young H.Cho

      May 2011 – Present

      • Low power VLSI using numerical analysis

    2. At Caltech - Prof.Alain J Martin

      May 2009 – Aug 2010

      • Design of robust soft error tolerant asynchronous memories and characterization of sub -nanometer technologies using foundry data, HSPICE and Cadence Composer/Virtuoso, Synopsis Calibre.

      • Analysis of manufacturing variations in sub nanometer technologies and their impact on VLSI design synthesis.

    3. At USC- Prof.Sandeep Gupta

      May 2011 – Present

      • Design of Hardware Intrusion Detection System

    4. At USC - Prof.Massoud Pedram

      Aug 2010 – Dec 2010

  • Teaching Assistant

    Jan 2010 – Present

    1. CSCI 558L: Internetworking and Distributed Computing Lab

    2. EE 599: Network Precessors

    3. EE 552: Asynchronous VLSI design

    4. EE 577B: VLSI System Design II

    5. EE658: Diagnosis and Design of Reliable Digital Systems.


  1. Simulation of Wireless network nodes on NetFPGA (BEST PROJECT AWARD)

    Tools Used: NetFPGA design suite

    Implemented hardware to simulate packet forwarding in wireless network nodes with packet dropping probability and successfully demonstrated expected results at the Stanford NetFPGA summer camp 2011.

  2. Automated Clock Gating

    Tools Used: Berkeley SIS, C

    Automatically synthesize and produce a gate-level net list that is "optimally" clock gated to minimize power over area overhead metric.

  3. Soft error tolerant asynchronous memories

    Tools Used: Cadence Composer/Virtuoso, HSPICE, Calibre

    Schematic, layout design of SEU tolerant SRAM with 6*64 row decoder, read/write circuitry, sense amplifiers etc.

  4. DDR2 Controller Design

    Tools Used: NCSim, NC-Verilog, Synopsys DC

    VerilogHDL design of DDR2 controller using Denali’s 512Mb software model based on JEDEC specs. Synt hesized in 0.18um technology using Synopsys DC.

  5. 5 stage Pipelined Processor design.

    Tools Used: EPD

    Design of a 5 stage pipelined processor to support in order execution of MIPS instructions taking care of RAW and Branch hazards.

  6. 2.048Kb SRAM Design in 0.18um tech.

    Tools Used: Cadence Composer/Virtuoso, HSPICE, Nanosim

    Schematic, layout design of SRAM with 6*64 row decoder, precharge, read/write c ircuitry, sense amplifiers ,etc.

  7. Hardware Design of 16-Bit Motion Estimator for a DSP

    Tools Used: Cadence Composer/Virtuoso, HSPICE, Nanosim

    Schematic, layout design of SRAM with 6*64 row decoder, precharge, read/write c ircuitry, sense amplifiers ,etc.

  8. Test Generation system for a FPGA chip family

    Language Used: C

    Designed an ATE for a circuit given in ISCAS’85 format. The major components of the test generation system designed and integrated are Preprocessor, Logic simulator, Fault simulator and an ATPG.

  9. IC Chip fabrication and electrical characterization

    Tools Used: IC fabrication lab, USC.

    Fabricated and characterized MOS resistors, capacitors, diodes and FET with a feature size of 1.2µm on Si (100) P -type substrate wafer.

  10. Design of Digital Neural Network

    Tools Used: Cadence Composer/Virtuoso, HSPICE

    Designed the digital neural network in both schematic and layout using cadence in 0.18um technology.

  11. 4X4 Asynchronous crossbar

    Tools Used: ModelSim

    Designed a 4X4 crossbar using VerilogCSP and optimized design for lowest latency.

  12. Shared Streaming - Indian Institute of Science, Bangalore.

    Tools Used: Visual C++

    Designed and integrated a streaming VOIP application into an existing peer -to-peer communication application.

Honors & Awards

  1. Best project award at the NetFPGA summer camp 2011 , Stanford University.
  2. Best Design award for the project "16 bit motion estimation kernel of a DSP" in a design contest at USC.
  3. Awarded "Thanks a Zillion" Award in Wipro Technologies at the General Motors CTO meet.